Electron beam lithography for 1 micron FET logic circuit fabrication

We describe the fabrication of 1 micron minimum linewidth FET polysilicon devices and circuits. These were designed for the tight dimensional groundrules achievable using direct wafer write scanning electron beam lithography. This paper emphasizes the vector-scan electron beam technology and processing, while other papers in this conference(1) discuss other aspects of the work. Different types of 1 micron FET chips were written on 57mm Si wafers using a totally automated electron beam system(2) which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance jumps between shapes. A novel two-layer positive resist system has been developed to achieve reproducible lift-off profiles over topography and better linewidth control (typically <0.1 micron). A level to level registration accuracy groundrule of 0.3 micron has been satisfied with achievement of typical alignment of 0.1-0.2 microns between any two levels.