A new technique to minimize the EPROM cell

This paper presents a new technique to minimize the UV Erasable, Electrically Programmable, Read-Only Memory (EPROM) cell based on N-channel double polysilicon gate MOS. The new technique features a fully self-aligned floating gate structure which reduces the EPROM cell size/bit to almost that of presently most advanced mask ROMs. A new fabrication process and the experimental results for both programming and erasure are presented. The dependence of characteristics on various device parameters are discussed with emphasis on the difference from conventional devices.