Abstract :
A novel structure of a negative resistance diode for high density static RAM cell is described. The diode, called Substrate-Fed CMOS (SF-CMOS) diode, consists of weak depletion type p- and n-MOSTs, whose drains are formed in the p-well and n-substrate, respectively. The structure enables supplying a diode current via substrate. Drain currents for the FETs, which operate in the subthreshold region, are controlled by back-gate bias, resulting in a sharp negative resistance with an "OFF" current below 1pA. The SF-CMOS diode plus a transfer-gate transistor and a load element make up a memory cell. The feasibility of using a polysilicon resistor, a leaky diode and a MOSFET for the load element is discussed. An eight-by-eight cell array of SF-CMOS cells with MOSFET loads is fabricated and examined. Using a 5µm line width and 3µm spacing design rule, the obtained cell size is 1440µm2, compared with 3000µm2required for a six-transistor cell. A 4096-word by 1-bit static RAM has been designed using SF-CMOS cells. The obtained chip size is as small as 14.9mm2. READ and WRITE operations of the RAM are similar to those of single transistor cells, except that SF-CMOS cells need no refresh operation. A 45 ns access time has been obtained with 5-volt VDD, using computer simulation.
