DocumentCode :
3554682
Title :
Novel high density, stacked capacitor MOS RAM
Author :
Koyanagi, M. ; Sunami, H. ; Hashimoto, N. ; Ashikawa, M.
Author_Institution :
Hitachi Ltd., Kokubunji, Tokyo, Japan
Volume :
24
fYear :
1978
fDate :
1978
Firstpage :
348
Lastpage :
351
Abstract :
A novel one transistor type MOS RAM cell is successfully developed and achieves a higher degree of integration than realized to date with conventional RAM´s. This cell provides remarkable area reduction and/or an increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This new cell has a triple level poly-Si structure of poly-Si word lines and Al bit lines. The stacked capacitor is composed of a poly-Si - Si3N4- poly-Si structure. A 256 bit STC MOS RAM is fabricated with 3 µm technology and operates successfully. The STC RAM cell area, 52.5 µm2, is remarkably smaller than the cell area of conventional RAM´s with double level poly-Si gate structure, 160 µm2.
Keywords :
Capacitance; Fabrication; Laboratories; Leakage current; MOS capacitors; MOSFETs; Random access memory; Read-write memory; Stacking; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1978 International
Type :
conf
DOI :
10.1109/IEDM.1978.189425
Filename :
1479850
Link To Document :
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