A high gain structure for power junction gate field effect transistors

A new planar, junction gate field effect transistor structure is described. The device structure is fabricated with steep vertically walled gate regions by using orientation dependent etching and epitaxial refill. Triode-type blocking characteristics are observed at higher gate bias voltages. Source-to-drain breakdown voltages exceeding 200 volts have been achieved with differential blocking gain greater than 30. These gains are much larger than those achieved in previous surface gate JFET structures.