Theoretical comparison of DMOS and VMOS structures for voltage and on-resistance

VMOS and DMOS vertical FETs are both viable high voltage structures. In these structures the critical design trade-off is between breakdown voltage and on-resistance. Part of the on-resistance is due to spreading resistance from the end of the channel into the drain. This portion of the resistance can be much reduced by intentional gate-drain overlap which, unfortunately, increases gate capacitance. In this paper it is found that a certain degree of overlap also increases breakdown voltage due to field plate effects. Hence, both VMOS and DMOS devices with overlap as one parameter are compared for both on-resistance (and capacitance) and breakdown voltage. Because of the importance to spreading resistance of the ratio of repeat distance to drain thickness this comparison is also done with repeat distance from 8 microns to 104 microns.