A new VMOS power FET

This paper describes the design of a new family of VMOS power FETs exhibiting low ON resistance, high current as well as high breakdown voltage and fast switching speeds. The design which is based on a 1st-order device model, features a novel polysilicon-gate structure and a field-plated groove termination to achieve high packing density and high breakdown voltage, respectively. One device measuring 0.19 cm²realizes a w/l ratio in excess of 750,000. It can block 200 V at an ON resistance of 0.1 ohm. This chip delivers over 50 A of pulsed drain current with 10 V gate drive. Another device measuring 0.15 cm²can sustain 450 V at 8 A of pulsed drain current, withstand a slew rate (dv/dt) of over 25 V per nanosecond, and switch 5 A in 30 nanoseconds.