Variable resistance polysilicon for high density CMOS RAM

A new and attractive structure of static RAM cell with a variable resistance polysilicon load, i.e. a polysilicon transistor load (PTL) has been developed. The resistance is controlled by "under gate" formed of underlying n⁺-layer. Symmetric p- and n-MOSFET actions of the undoped polysilicon transistor are observed and theoretically analyzed. The PTL, operating as a p-MOSFET, enables data storage with a current as low as 10^-10ampere per bit. The PTL conductance in an "ON" state is high enough to overcome fabrication process fluctuations or radiation stimuli. Utilizing n⁺-layer interconnections under the polysilicon, a small cell size of 899µm², which is comparable to conventional polysilicon load four-transistor cells, is achieved with a 3µm design rule. Test memory arrays have been fabricated and READ/WRITE operations are successfully verified.