Performance of downward scaled CMOS/SOS

MOS/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS/ SOS devices. Furthermore, short channel CMOS/SOS device performance has been discussed in comparison with the CMOS/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through current between the source and drain. Also, deeper phosphorus implant was used for p-channel MOSFET on SOS to reduce the punch through current. Shallow boron implant was also used to adjust the threshold voltage to the desired value for both n- and p-channel devices. This design is especially beneficial for downward scaled CMOS/SOS devices. Using this device structure, short channel CMOS/SOS devices have been successfully fabricated. Comparison of the experimental results with CMOS/SOS ring oscillator computer simulation has made it clear that the wiring capacitance will play a predominant role in determining the speed of a device with shorter channel length. Superiority of SOS in speed should be emphasized in smaller feature size devices, due to its essentially smaller wiring capacitance than bulk devices.