Title :
Splicer: a heuristic approach to connectivity binding
Author :
Pangrle, Barry M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix
Keywords :
circuit layout CAD; heuristic programming; logic CAD; 4.2 BSD Unix; C code; CAD; Splicer; connectivity binding; high level synthesis; layout; state graph; Buildings; Filling; Flow graphs; Hardware; High level synthesis; Programmable logic arrays; Read only memory; Read-write memory; Silicon compiler; Synthesizers;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14812
