Simulating VLSI wafer topography

As dimensions of the classical "planar" process are reduced the device features in the third dimension pose major fabrication and performance problems. Establishing techniques to characterize and optimize these non-planar device features is a primary goal of research on modeling and simulation. Lithography, etching and deposition models have been established which agree well with experiment. In many cases the dominant physical mechanism is a surface reaction process which can be simulated by a surface advancing algorithm such as the cell, ray or string approach. Prime examples of the usefulness of simulation are in understanding projection printing, step coverage in deposition, wafer planarization and linewidth bias and control for composite process sequences. Simulations for individual IC fabrication processes are being combined in a user oriented program for Simulation And Modeling of Profiles in Lithography and Etching (SAMPLE).