DocumentCode
3555166
Title
Process modeling of multilayer structures involving polycrystalline silicon
Author
Mei, Len ; Swaminathan, Balaji ; Dutton, Robert W.
Author_Institution
Stanford University, Stanford, Calif.
Volume
26
fYear
1980
fDate
1980
Firstpage
219
Lastpage
222
Abstract
A process model capability has been developed to simulate the electrical and metallurgical parameters of multilayer structures involving polycrystalline Silicon, such as poly gate and buried contacts. Experimental and simulated results are shown for poly interconnection lines on oxide and buried contacts to bulk Silicon. The simulation of poly processing effects including the instantaneous oxidation rate, the penetration of impurities through the gate oxide and sheet resistivity of poly interconnects, as well as the impurity profiles in the buried contact structures are discussed.
Keywords
Conductivity; Contacts; Doping; Grain size; Impurities; Integrated circuit interconnections; MOS devices; Nonhomogeneous media; Semiconductor process modeling; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1980 International
Type
conf
DOI
10.1109/IEDM.1980.189798
Filename
1481241
Link To Document