Title :
A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process
Author :
Masuoka, F. ; Ariizumi, S. ; Fukatsu, Y. ; Nishimura, H.
Author_Institution :
Toshiba Corporation Ltd., Kawasaki, Japan
Abstract :
A new memory cell structure with a new fabrication process which enables to obtain the resistor with smaller dimension is proposed. The memory cell has been successfully applied to a high performance 16K bit MOS static RAM using a conventional design rule. A new fabrication process and characteristics of the device elements and a high speed 2k × 8 bit NMOS static RAM are described.
Keywords :
Conductivity; Fabrication; Impurities; Ion implantation; Joining processes; MOS devices; Random access memory; Read-write memory; Resistors; Voltage;
Conference_Titel :
Electron Devices Meeting, 1980 International
Conference_Location :
Washington, DC, USA
DOI :
10.1109/IEDM.1980.189901
