Interaction of IGFET field design with narrow channel device operation

The effects of decreasing FET channel width as reported by previous workers reveal three basic mechanisms: Increase in current drive due to voltage gradients at channel width edge tapers; increase in threshold voltage due to the two dimensional aspects of the transition of channel depletion region to field oxide region; and the effect of field doping encroachment at channel edges. An independent investigation reported in this paper shows that for high resistivity substrate poly-gate FET technologies, the last mechanism has a strong dependence on the device´s effective width, which varies not only with the gate-to-source bias but also with substrate back bias. Junction edge capacitance and breakdown voltages are also affected. To dimensional simulations qualitatively substantiate these observed effects. It is concluded that the cause of these effects and its variability can be attributed to both photo and hot process steps. The resultant trade-off between density and device performance is discussed in regard to its implications for present and future FET technologies.