Variable taper CMOS buffer design

Author

Vemuru, Srinivasa R ; Smith, Edwyn D.

Author_Institution

Dept. of Electr. Eng., Toledo Univ., OH, USA

fYear

1991

fDate

12-14 Jun 1991

Firstpage

179

Lastpage

184

Abstract

A variable taper (VT) approach is proposed for the design of CMOS buffers. The minimum propagation delay obtained by using a VT buffer is approximately 12% higher than the minimum propagation delays obtained by using a conventional fixed taper (FT) approach. A modification to the initial stages of a VT buffer reduces this difference to within 2% of a FT buffer. For buffer designs with similar propagation delays, a VT buffer design usually takes significantly less silicon area and dissipates less power

Keywords

CMOS integrated circuits; buffer circuits; delays; integrated logic circuits; logic design; CMOS buffer design; minimum propagation delay; variable taper; Capacitance; Computational geometry; Delay estimation; Driver circuits; Integrated circuit synthesis; Inverters; Logic circuits; Power dissipation; Propagation delay; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1991. Proceedings., Ninth Biennial

Conference_Location

Melbourne, FL

ISSN

0749-6877

Print_ISBN

0-7803-0109-9

Type

conf

DOI

10.1109/UGIM.1991.148146

Filename

148146

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3555372