DocumentCode :
3555375
Title :
A full-wafer SOI process for 3 dimensional integration
Author :
Subramanian, Chitra K. ; Neudeck, Gerold W.
Author_Institution :
Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
1991
fDate :
12-14 Jun 1991
Firstpage :
195
Lastpage :
198
Abstract :
A full-wafer silicon-on-insulator (SOI) process using epitaxial lateral overgrowth is demonstrated. Merged selective epitaxial growth of silicon was used to create local area SOI islands. Chemical-mechanical polishing was used to form well-controlled submicrometer-thick single-crystal SOI film using local area nitride as etch stops. Epitaxial lateral growth which was initiated from a vertical seed is demonstrated. The technique produces a generic full-wafer SOI structure. To obtain multiple layers of silicon over oxide, this SOI process can be repeated several times without damage to the previously formed layers and therefore makes three-dimensional integration possible
Keywords :
semiconductor epitaxial layers; semiconductor growth; semiconductor-insulator boundaries; 1 micron; 3D IC; 3D integration; Si-SiO2; chemical mechanical polishing; epitaxial lateral overgrowth; etch stops; full-wafer SOI process; local area SOI islands; local area nitride; multiple layers; selective epitaxial growth; single crystal film; three-dimensional integration; vertical seed; CMOS technology; Circuits; Costs; Etching; Insulation; MOSFETs; Silicon on insulator technology; Substrates; Very large scale integration; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 1991. Proceedings., Ninth Biennial
Conference_Location :
Melbourne, FL
ISSN :
0749-6877
Print_ISBN :
0-7803-0109-9
Type :
conf
DOI :
10.1109/UGIM.1991.148149
Filename :
148149
Link To Document :
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