• DocumentCode
    3555378
  • Title

    Characterization and elimination of threshold voltage problems in the Bimos process

  • Author

    Dean, Steven J.

  • Author_Institution
    Harris Semiconductor, Findlay, OH, USA
  • fYear
    1991
  • fDate
    12-14 Jun 1991
  • Firstpage
    204
  • Lastpage
    209
  • Abstract
    The author identifies two root causes and a number of special causes of high-P/low-N threshold voltage in the Bimos process. The first root cause was chemical carryover from wafer carriers exposed to HF. the F- retained in the carrier can hydrate, form a vapor, and condense on the wafer. This phenomenon was the source of a large amount of unexplained high-P threshold problems in the past. The second root cause was oxide charge being introduced at the trim anneal furnace operation. Increasing the N2 flow brought a major yield loss problem under control. since the two root causes have been eliminated, there have been no significant threshold voltage problems with this technology
  • Keywords
    BIMOS integrated circuits; annealing; integrated circuit manufacture; integrated circuit technology; BIMOS process; F- ion carryover; N2 flow increase; characterisation; chemical carryover; oxide charge; problem solving; root causes; special causes; threshold voltage problems elimination; trim anneal furnace operation; yield loss problem; Bipolar transistors; Circuit testing; Doping; Fabrication; Furnaces; MOS devices; Silicon; Substrates; Surface contamination; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    University/Government/Industry Microelectronics Symposium, 1991. Proceedings., Ninth Biennial
  • Conference_Location
    Melbourne, FL
  • ISSN
    0749-6877
  • Print_ISBN
    0-7803-0109-9
  • Type

    conf

  • DOI
    10.1109/UGIM.1991.148151
  • Filename
    148151