DocumentCode
3555430
Title
Design for alpha immunity of MOS dynamic RAM´s
Author
Mitsusada, Kazumichi ; Katto, Hisao ; Toyabe, Toru
Author_Institution
Hitachi, Ltd., Tokyo, Japan
Volume
27
fYear
1981
fDate
1981
Firstpage
36
Lastpage
39
Abstract
Soft error rate(SER) analysis model named HSERAM has been developed to provide a design tool for alpha immunity of MOS dynamic RAM´s. The model is verified through the good agreement between the simulated and the measured SER of 64K bit dynamic RAM´s. The SER of the metal folded-bit-line structure is compared around 10 times favorably with that of the diffused open-bit-line one in case of the same signal charge. Accelerated testing with increased alpha flux is risky for bit line mode soft error with large signal charge because of few alpha particles of low angle incidence which are most harmful in package mounted devices. Also shown briefly are the effectiveness of a protective coating to reduce SER and the measurement techniques easily equipped to detect 10-5ppm level of U and Th in semiconductor component materials.
Keywords
Alpha particles; DRAM chips; Electrons; Error analysis; Error correction; Insulation; Protection; Read-write memory; Semiconductor device packaging; Semiconductor materials;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1981 International
Type
conf
DOI
10.1109/IEDM.1981.189992
Filename
1481945
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