A buried N-grid for protection against radiation induced charge collection in electronic circuits

We show that the soft-error rate (SER) in integrated circuits may be reduced by a structural modification which decreases the amount of charge collected in sensitive nodes. A protective structure, consisting of an electrically floating grid of n-type Si buried ∼2.2 m below the surface in a p-type substrate, has been fabricated and is demonstrated to be an effective shield against the collection of radiation-induced carriers in circuit nodes. A fabrication technique requiring two high energy ion-implants and one masking step is described. The grid is shown to block as much as 85% of the charge that would normally be collected in a 17 m x 1700 m diode hit by a 4.5MeV α-particle. The corresponding reduction in SER for a 1 m DRAM is calculated to be a factor of 5.