A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI

The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 0.2 µm gate length including all of the major effects such as source/ drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different scaling schemes which are based on different power supply scenarios. From the degradation factor of triode gain and drain saturation current, the relative contribution of each parasitic effect on device performance degradation has been examined. Based on these calculations, some modifications to straightforward scaling are considered.