DocumentCode
3555490
Title
A new two task algorithm for clock mode fault simulation in sequential circuits
Author
Hill, Fredrick J. ; Abuelyamen, Eltayeb ; Huang, W.-K. ; Shen, G.-Q.
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear
1988
fDate
12-15 June 1988
Firstpage
583
Lastpage
586
Abstract
A novel approach to clock-mode simulation of sequential circuits is introduced. Surrogate fault propagation is used for processing stored faults and extracting new faults from combinational logic. Problem fault types are analyzed and treated as exceptions.<>
Keywords
clocks; logic testing; sequential circuits; clock mode fault simulation; combinational logic; sequential circuits; stored faults processing; surrogate fault propagation; two task algorithm; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Computer simulation; Logic design; Logic testing; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14820
Filename
14820
Link To Document