DocumentCode
3555534
Title
Design model for bulk CMOS scaling enabling accurate latch-up prediction
Author
Wieder, Armin W. ; Werner, Christoph ; Harter, Johann
Author_Institution
Siemens AG, Munich, F.R.Germany
Volume
27
fYear
1981
fDate
1981
Firstpage
354
Lastpage
358
Abstract
An a priori model for CMOS design including latch-up prediction is presented. It is based on rigorous numerical 2-D simulations as well as on experimental data and gives accurate bulk-CMOS-scaling rules.
Keywords
CMOS technology; Charge carrier processes; Doping; Laboratories; Latches; Numerical simulation; Poisson equations; Predictive models; Semiconductor device modeling; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1981 International
Type
conf
DOI
10.1109/IEDM.1981.190086
Filename
1482039
Link To Document