Direct moat isolation for VLSI

A direct moat isolation approach which overcomes scalability limitation of local oxidation of silicon (LOCOS) is discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 µm.