Perspective of scaled bipolar devices

To predict the performance of future bipolar VLSIs, practical 2-dimensional device simulator has been developed, in which bandgap narrowing and Auger recombination at high impurity concentration are taken into consideration, and in which the conductivity modulation caused by excess minority carriers is modelled analytically. Procedure for optimizing the vertical transistor structures is described in terms of breakdown voltage. Relation between base impurity concentration and base width to give a necessary breakdown voltage is obtained from the numerical analysis including statistical doping fluctuations. According to the simulation of ECL circuit with 3V power supply, less than 100pS per gate is achievable when the device is scaled down to 0.5µm emitter stripe width and 0.056µm base width. It is concluded that the performance of submicron bipolar devices is enough competitive with that of GaAs MESFET devices.