CATAPULT: concurrent automatic testing allowing parallelization and using limited topology

Author

Gaede, Rhonda Kay ; Mercer, M. Ray ; Butler, Kenneth M. ; Ross, Don E.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1988

fDate

12-15 June 1988

Firstpage

597

Lastpage

600

Abstract

An improved algorithm is presented for identifying redundant faults and finding tests for hard faults in combination circuits. A concurrent approach is proposed which is based on the concepts of functional decomposition, explicit representation of fanout stems, and the Boolean difference. The data structure used is the binary decision diagram. The algorithm operates as a back end to test generators which use random patterns or heuristics or a combination of the two.<>

Keywords

automatic testing; combinatorial circuits; logic testing; Boolean difference; CATAPULT; binary decision diagram; combination circuits; concurrent automatic testing; data structure; explicit representation; fanout stems; functional decomposition; hard faults; logic testing; test generator back end; Automatic test pattern generation; Automatic testing; Boolean functions; Circuit faults; Circuit testing; Circuit topology; Costs; Data structures; Fault diagnosis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-8186-0864-1

Type

conf

DOI

10.1109/DAC.1988.14823

Filename

14823