DocumentCode
3555677
Title
A graph compaction approach to fault simulation
Author
Harel, Dov ; Krishnamurthy, Balakrishnan
Author_Institution
Tektronix Inc., Beaverton, OR, USA
fYear
1988
fDate
12-15 June 1988
Firstpage
601
Lastpage
604
Abstract
The authors describe a graph-compaction-based algorithm for fault simulation in combination circuits. The algorithm consists of reducing the circuit graph by repeatedly removing nonreconvergent vertices. The algorithm has been implemented in Smalltalk and preliminary experimental results are presented. A version of the algorithm outperforms all known fault simulation algorithms on a family of hard circuits.<>
Keywords
combinatorial circuits; graph theory; logic testing; Smalltalk; combination circuits; fault simulation; graph compaction; logic testing; nonreconvergent vertices; Algorithm design and analysis; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Compaction; Computational modeling; Decoding; Fault detection;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14824
Filename
14824
Link To Document