High voltage NMOS switching array with active pull-ups and low voltage addressing logic

This paper describes a unique, fully integrated NMOS device capable of operation at 500 volts. The chip consists of 16 active, pull-up devices, 16 corresponding pull-down drivers, a 16 bit shift register with latch for serial to parallel conversion and gating logic. Each high voltage switching pair employs transistors with closed geometry, polysilicon field plates, resistive circuit elements and capacitive bootstrapping. No deep diffusion, epitaxial layer or dielectric isolation is required. The low voltage logic is comprised of conventional NMOS components and drives the high voltage devices directly. It is isolated from the high voltage areas by grounding rings and operates from TTL voltage levels. The HVMOS switching array has been fabricated and tested. Results indicate that the high voltage fall time is less than 1 us and the rise time is less than 4 us with minimal loading (50 pF). Operation at 500 volts was achieved and quiescent power for the array was less than one watt. Current carrying capability for both the pull-up and pull-down devices exceeds 25 mA and operation above 70 degrees C. was demonstrated. Overall chip size is 205 × 229 mil²housed in a conventional 28 pin DIP. The principal applications for such arrays are in displays and electrographic printers. This paper will discuss the HVMOS switching pair in detail along with the fabrication process and performance parameters. Unique features of this design will be highlighted. Stress tests, which demonstrate good stability and reliability, will also be discussed.