A high speed signal processor by the device scaling

Operation speed improvement of a digital signal processor of N-channel enhancement/ depletion circuit type, has been realized by the application of the device scaling technology. The original version of the signal processor with 3.1 micron design rule has been scaled down simply into the two versions with 2.5 and 2.0 micron design rules. With this scaling down, the operation clock frequency, 11 MHz in original version, has been improved to 18 MHz and 21 MHz, respectively. From this investigation, an experimental relation that the power-delay product of a microprocessor is almost proportional to the 1.5-th power of the scaling factor has been derived in association with the similar experiments on other CPU´s, instead of the third power law predicted from the simple theory.