Isolation technology for scaled MOS VLSI

Local oxidation with self-aligned field threshold implant has become pervasive as the technique for device isolation in n-channel Si-gate technology. As device dimensions approach 1µm, both geometrical and performance limitations demand reconsideration of this choice. In this paper the goals and limitations of device isolation technology (threshold control, step coverage, transition region size, complexity) are first examined, and the various alternatives which have been proposed are critically reviewed. It appears that several evolutionary developments can significantly extend the life of conventional isolation technology.