Electrical properties of MOS devices made with SILO technology

The physical and electrical parameters of Sealed Interface Local Oxidation (SILO) technology are explored in this paper. Devices fabricated with SILO technology and a standard NMOS process are characterized for current drive capability and parasitic effects. MOS transistors (W/L=3/20) show a 68% improvement in current density compared to devices of the same geometry fabricated with conventional local oxidation technology. Extensive electrical characterization on SILO devices shows that junction leakages and transistor sidewall leakages are low and comparable to devices fabricated with a conventional LOCOS process. Crystal defect decoration studies are in agreement, showing no defect generation.