Topography dependent electrical parameter simulation

The effect of wafer topography on the resistance and interlayer capacitance of deposited films is simulated from SAMPLE deposition profiles using a new post processor called RACPLE. The algorithm recognizes key profile features and is accurate to better than 5%. Geometrical step coverage effects are shown to increase resistance, capacitance and RC delay by an order of magnitude for high aspect ratio VLSI. These effects are a strong function of the deposition method. The importance of new deposition methods in achieving a scalable technology is illustrated.