Surface induced latch-up in VLSI CMOS circuits

Experimental and simulated results of the gate influence on latch-up in CMOS with and without epitaxy are presented. While in CMOS without epitaxy latch-up is bulk initiated, in structures with an epitaxial layer latch-up is essentially surface controlled. The critical latch-up current in this case is two orders of magnitude higher. The strong surface effect observed is a consequence of the gate influence on avalanche breakdown, on surface conduction of the field oxide MOSFET´s and on current gains of the bipolar transistors. In reducing the lateral dimensions, short channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.