To achieve high frequency performance in a transistor, along with low parasitics, the intrinsic device should have very low transit time of carriers from source to the drain. We report on the fabrication and D.C. characterization of vertical transistors with 0.5

m drain to source spacing and with sub-

m channel widths. A g
mof 81 mS/mm was achieved in the devices doped at

cm
-3and 47 mS/mm in those doped at

cm
-3. We propose this structure as a convenient method of studying the influence of near-ballistic electron motion on transistor performance.