A 55ns 64K dynamic MOS RAM with tripple diffused MOS transistor

To obtain the higher performance dynamic MOS RAM, there exist three key parameters for device technologies. The higher performance transistor, the lower resistance interconnections and the smaller stray capacitance realize a high speed and low power operation. The tripple diffused MOS transistor (T.D.T) which satisfies these requirements has been proposed. A novel 64K dynamic MOS RAM with a tripple diffused structure of 2.0 m gate length has been successfully fabricated. A typical access time of 55nsec was obtained at the power dissipation of 150mW. This excellent electrical characteristics was become possible by the tripple diffused MOS transistor which reduced the short channel effects, the gate to source/drain overlap capacitance and the parasitic resistance.