High speed 1 µm CMOS technology

In order to pursue high speed performance of CMOS logic gates, 1µm CMOS technology has been realized by using advanced process technologies. CMOS logic gate arrays, with minimum feature size of 1.1µm, were prepared, and their operation speed performances were evaluated. Delay times per gate of 0.1 - 0.2 ns have been observed in CMOS logic arrays of 3NAND, 3NOR and F/O=3 INVERTER arrays, of 1.1µm design rule. To realize those logic arrays, 1µm double-well CMOS basic technology has been developed. In this paper, process technology, electrical characteristics of N-channel and P-channel transistors, and device operation characteristics of the CMOS logic arrays, are described.