Design and fabrication of p-channel FET for 1- µm CMOS technology

A retrograde n-well is shown to be good for 1-µm bulk CMOS technology using n⁺polysilicon gates. P-Channel FET´s with a threshold voltage of -0.6V fabricated in a retrograde n-well show small short-channel threshold lowering and good turn-off characteristics. In these devices thermally formed TiSi2is self-aligned to the shallow (0.3 µm) source/drain region to reduce the sheet resistance to 4 ohms/square. Because contact resistance from TiSi2to p⁺is a dominant factor in the total parasitic resistance from metal to the FET channels, high surface doping concentration of S/D regions is still preferred.