Titanium disilicide self-aligned source/drain + gate technology

Silicides have been used to lower the resistance of gate level interconnects. Recently silicidation of source/drain diffusions have also been reported. In scaled CMOS devices, silicidation of source/drains is particularly important in reducing the sheet resistance of p+ source/drain diffusions. In this paper, a novel technique is described in which TiSi2is formed self-aligned to both source/drain and gate regions. Both n and p-channel MOSFETs Silicided with self-aligned TiSi2on source/drains gates have been fabricated using this technique. Sheet resistances below 5 Ω/□ on both gate and source/drain levels have been achieved and thus represent at least a 10X reduction in the resistance of p⁺diffusions. Diode leakage, subthreshold leakage, and threshold voltage measurements on silicided devices are comparable to that of control devices without silicidation, CMOS circuit applications of this TiSi2self-aligned source/drain and gate technology are discussed.