DECOMPOSER: a synthesizer for systolic systems

Author

Hou, Pao-Po ; Owens, Robert Michael ; Irwin, Mary Jane

Author_Institution

Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA

fYear

1988

fDate

12-15 June 1988

Firstpage

650

Lastpage

653

Abstract

A tool for synthesizing systolic systems is introduced. Given a hierarchical specification of the computations to be performed and hints as to how, this tool generates an analysis of the hardware required to the computations. The computations are specified as directed acyclic graphs, and the hints provide the temporal and topological relationships of each computation. The systolic system is synthesized by traversing the graph and marking each computation with a processor name and a time stamp. Its output can subsequently be fed to the remaining tools in the tool set to generate a VLSI fabrication description of the systolic system.<>

Keywords

VLSI; circuit layout CAD; logic CAD; network topology; user interfaces; CAD; DECOMPOSER; VLSI fabrication description; directed acyclic graphs; hierarchical specification; hints; layout design; logic design; synthesizer; systolic systems; topological relationships; user interface; Computer science; Digital signal processing; Fabrication; Hardware; Performance analysis; Pipeline processing; Process design; Signal synthesis; Synthesizers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-8186-0864-1

Type

conf

DOI

10.1109/DAC.1988.14835

Filename

14835