Directions in CMOS technology

This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region. In that context, the authors review bulk CMOS technology from 2µm to sub-micron features based upon existing device characteristics, and also discuss directions for further downward scaling.