Characterization and modeling of transient latchup in CHMOS technology

This paper presents the experimental results of transient latchup initiation measured on various test structures and pulsing conditions in the CHMOS III technology. A simple model is developed to simulate the measured transient latchup initiation characteristics. This model includes the junctions and well capacitances as well as the intrinsic transient delay of the parasitic transistors of the latchup SCR. The simulation results of this model agree with the experimental data and indicate that the transient dependence of the latchup initiation in the CHMOS III technology has a time constant proportional to the SCR transistors base transit times and the RC time constant of the distributed capacitances in the well and the substrate. The application of these results in the design of latchup free dynamic circuits optimized for high speed performance and dense layout is demonstrated on CHMOS dynamic random access memories.