DocumentCode
3556015
Title
SMART: tools and methods for synthesis of VLSI chips with processor architecture
Author
Bergstraesser, T. ; Gessner, J. ; Hafner, K. ; Wallstab, S.
Author_Institution
Siemens AG, Munich, West Germany
fYear
1988
fDate
12-15 June 1988
Firstpage
654
Lastpage
657
Abstract
A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<>
Keywords
VLSI; circuit CAD; logic CAD; CAD; Common Lisp; SMART; VLSI chips; behaviour structure-representation; data-path style; design environment; hardware structure; interactive graphical manipulation; logic design; processor architecture; processor synthesis; programming model; Automatic testing; Circuit synthesis; Circuit testing; Data structures; Hardware; Information technology; Integrated circuit synthesis; Process design; Production; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14836
Filename
14836
Link To Document