An automated methodology for generating self-consistent layout rules for VLSI designs

A methodology for automatically generating self-consistent layout groundrules is presented. The methodology uses electrically measured data on misalignment tolerances and critical dimensions as inputs for the calculation of layout groundrules. Examples of layout groundrules constrained by electrical, lithographic or reliability reasons will be shown. Sample groundrules will be constructed using the different components that make up the groundrule. Critical dimension data and misalignment data will be shown that demonstrate common pitfalls in the measurement of the data. A computer program that calculates each groundrule is briefly described and is shown to have utility in being, able to quickly define a complete set of layout groundrules based on updated misalignment and critical dimension data. The end result of this methodology produces a set of self-consistent layout groundrules where no single layout rule will be more difficult to make than any other layout rules.