A submicron CMOS megabit level dynamic RAM technology using doped face trench capacitor cell

Process technologies for megabit level dynamic RAMs are presented emphasizing submicron channel length MOSFET characteristics and cell size reduction. N-well CMOS composed of 0.5µm n-and 0.9µm p-channel length MOSFETs are used for peripheral circuits which operate at 3V. A Trench capacitor of which face is doped with phosphorus (Doped Face Trench Capacitor) is utilized to increase a cell capacitance and to ground the cell plate. The feasibility of these technologies for megabit level dRAM are verified by a submicron 256K dRAM fabrication.