DocumentCode
3556059
Title
High speed 1 µm SOS CMOS devices using double solid-phase epitaxy
Author
Yoshida, M. ; Nakahara, M. ; Kimura, M. ; Taguchi, S. ; Maeguchi, K. ; Tango, H.
Author_Institution
Toshiba Corporation, Kawasaki, Japan
fYear
1983
fDate
5-7 Dec. 1983
Firstpage
372
Lastpage
375
Abstract
High speed, highly reliable CMOS/SOS structure have been investigated from the view point of the realization of 1 µm CMOS/SOS VLSI devices. Double solid-phase epitaxy (double SPE) was used to improve the crystalline quality of thin SOS films, and lightly doped N-drain structure using side-wall formation technology was applied to scaled down CMOS/SOS devices. Remarkable improvement has been achieved for the lightly doped N-drain NMOS FETs compared with the conventional N+drain structure, which are the suppression of hot electron injection into the gate oxide and also the increase of the lateral bipolar breakdown voltage caused from the avalanche ionized hole injection into floating substrate. Furthermore, 1 µm double SPE CMOS/SOS speed performance has been discussed using ring oscillators in comparison with the as-grown film device. The 78 ps stage delay and the 0.24 mW stage power dissipation were successfully obtained by double SPE CMOS/SOS devices with N-drain structure on 0.3 µm thick SOS films.
Keywords
CMOS technology; Crystallization; Delay; Epitaxial growth; FETs; MOS devices; Ring oscillators; Secondary generated hot electron injection; Substrate hot electron injection; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1983 International
Conference_Location
Washington, DC, USA
Type
conf
DOI
10.1109/IEDM.1983.190519
Filename
1483644
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