Lateral DMOS transistor optimized for high voltage BIMOS applications

Optimal placement of buried layer under a LDMOS transistor extends the usefulness of the device in high voltage BIMOS integrated circuits. Coupling the resurf effect and gate-underlaid concept results in a LDMOS transistor with uncompromised high voltage characteristics: Source-drain avalanche breakdown greater than 300 V and channel-substrate punchthrough breakdown greater than 200 V. The process utilized to fabricate the high voltage LDMOS transistor is a junction isolated epitaxial process, This enables high speed Emitter Function Logic and high voltage driver capability to be implemented on the same integrated circuit. Process modifications and device design necessary to realize the high voltage gate underlaid LDMOS transistor are described. A novel method for calculating the collector-emitter breakdown of NPN transistors is presented in order to compare process requirements of high voltage NPN and LDMOS transistors. A high voltage plasma driver with high speed logic capable of clocking at rates over 20MHz demonstrates the versatility of the process and the optimized LDMOS transistor.