A high performance CMOS technology with Ti-Silicided p/n-type poly-Si gates

A Ti-silicided CMOS technology, to be applied to P/N-type CMOS in which gate poly-Si for p-channel and n-channel transistors is doped to p⁺and n⁺, res pectively, has been developed to enhance the integration packing density and speed performance. With this Ti-silicided P/N-type CMOS technology, sheet resistance is reduced to ∼ 2 ω/□ , which is 1/20- 1/50 Of non-silicided poly-Si gate electrodes, improves the RC delay time, buried contacts used for p-channel and n-channel transistors results in higher packing density, and no need of Al wiring between p-type and n-type poly-Si also results in higher packing density. This technology was exercised successfully in the fabrication of an 8 bit CPU.