DocumentCode
3556102
Title
Fabrication demonstration of 1-1.5 µ NMOS circuits using optical tri-level processing technology
Author
Orlowsky, K.J. ; Speeney, D.V. ; Hu, E.L. ; Dalton, J.V. ; Sinha, A.K.
Author_Institution
Bell Telephone Laboratories, Murray Hill, New Jersey
fYear
1983
fDate
5-7 Dec. 1983
Firstpage
538
Lastpage
541
Abstract
An improved optical (DSW) tri-level processing technology was utilized to produce a variety of high-performance 1-1.5µ NMOS circuits, including (a) functionally perfect chips of a 4K SRAM with estimated access times of 5 nsec, (b) 16-bit multiplier chips with multiply times of 21-40 nsec (clock rate, 47-25 MHz), and (c) optical fiber amplifier chips operating at 800 Mbit/sec.
Keywords
Circuits; Clocks; Delay; High speed optical techniques; MOS devices; Optical buffering; Optical design; Optical device fabrication; Preamplifiers; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1983 International
Conference_Location
Washington, DC, USA
Type
conf
DOI
10.1109/IEDM.1983.190562
Filename
1483687
Link To Document