Bipolar process technology evaluation by 3-dimensional device simulation

The optimization scheme of bipolar process technology in terms of propagation delay time is discussed, using multilayer metallization and self aligned transistor process. Studied is the loaded EF-ECL circuit with 3mm wiring length and 3 fan-out, assuming a maximum power dissipation of 10W for internal circuits. 4 different bipolar processes are evaluated, which are a 1µm conventional transistor and a 1µm self aligned structure with 3 or 4 layer metallization. At low current level, 4-layer metallization improves the switching speed by 24% compared with the 3-layer, and at high currents, 17% of the speed is reduced by the self aligned devices. If these two processes are combined, ultra high speed of 0.2nS for 2k gates and 0.6nS for 10k gates are attainable. The results indicate that the performance of the bipolar LSIs is competitive enough with that of GaAs MESFET because of the logical function capability of EF-ECL circuitry.