DocumentCode :
3556116
Title :
Design considerations for scaling FLOTOX E2PROM cell
Author :
Lee, Jimmy ; Dham, Vinod K.
Author_Institution :
Intel Corporation, Santa Clara, California
Volume :
29
fYear :
1983
fDate :
1983
Firstpage :
589
Lastpage :
592
Abstract :
The design considerations for scaling the FLOTOX E2PROM cell are presented in this paper. The smaller cell can be achieved by optimizing the programming voltage, reducing the interpoly coupling capacitor and scaling the tunnel dielectric thickness. To maintain the high reliability of the scaled cell the electric field stress during both programming and storage need to remain constant in scaling. An empirical model was developed to aid the design of various cell parameters. The impact on the read disturb due to a thinner tunnel dielectric is also examined. The read disturb can be eliminated by properly designing the gate and drain voltages during read.
Keywords :
Capacitance; Capacitors; Dielectrics; Maintenance; PROM; Semiconductor device manufacture; Semiconductor memory; Stress; Tiles; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1983 International
Type :
conf
DOI :
10.1109/IEDM.1983.190575
Filename :
1483700
Link To Document :
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