Title :
A channelless, multilayer router
Author_Institution :
Lawrence Livermore Nat. Lab., CA, USA
Abstract :
The authors have implemented a channelless, gridless, multilayer router as part of the Magic IC layout system. The router is designed to handle routing problems associated with emerging technologies such as wafer-scale integration and multilayered metal processes. Three features distinguish this router: rectilinear Steiner trees with floating segments a routing scheduler, and a corner-stitched database
Keywords :
circuit layout CAD; integrated circuit technology; network topology; CAD; Magic IC layout system; corner-stitched database; floating segments; multilayered metal processes; rectilinear Steiner trees; routing scheduler; wafer-scale integration; Automata; Integrated circuit layout; Laboratories; Nonhomogeneous media; Pins; Routing; Spatial databases; Topology; Wafer scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14839
